The Instruction Set Edition
On the IBM System/360, microarchitectures, and sanctions
Guan Yang (GY) is a data scientist based in New York. His favorite instruction set is IBM’s POWER. He previously wrote the Bitcoin Accounting Edition for WITI.
Guan here. 57 years ago, in April 1964, IBM announced the System/360 line of mainframe computers. At the time it was the costliest private development project in history, at $5 billion (about $43 billion today), more than the Manhattan Project. The line was hugely successful and introduced many new technologies in commercial use, including the 8-bit byte, 32-bit words, and the use of microcode in computer processors. The Mythical Man-Month, known to many software developers, was based on Fred Brooks’s experiences on the System/360 operating system project.
System/360 also introduced the idea of an instruction set architecture, or ISA. Computers exist to follow instructions, most of which involve doing arithmetic or logic, or moving data around between memory locations. Here’s an example of a System/360 instruction:
LR R15, R12 “load the contents of register 12 into register 15”
This is encoded as 18fc in hexadecimal in machine code. A “register” is a small, very fast piece of memory, and operations often happen on registers rather than main memory.
IBM announced seven different models of System/360 computers for different market segments in 1964. All of them supported the same instructions. Previous computers tended to use a custom instruction set created for that model, a trend that continued in the low-end market for a while after System/360. Later, Amdahl, Hitachi and RCA and others would make computers compatible with System/360 instructions.
To this day, many 1960s-era programs can run unmodified on new IBM mainframes. Today, customers in all but the most specialized applications expect new computers to support some common instruction set, so code and tools can be reused from other products using the same instructions.
Why is this interesting?
For a while, instruction sets weren’t that interesting, as long as the choice wasn’t too niche. Your home WiFi router is likely to use MIPS and many cars have chips that use SuperH, two instruction sets you’ve likely never heard of. Wii U game consoles use PowerPC instructions; Arduinos use AVR.
When Apple switched from IBM PowerPC to Intel x86 chips in 2006, the decision was driven by PowerPC chips of that era falling behind Intel on performance and efficiency. The x86 instruction set was already viewed as technically inferior, but Intel made higher performance processors by recasting the instructions as simply an interface to a radically different microarchitecture under the hood. Using the terminology of higher-level programming: the instruction set is an API to the hardware, with underlying implementations increasingly decoupled from what you might guess just by looking at the API.
For the past decade, if you’re making a new custom chip, the go-to was one of the offerings from ARM, a British company now owned by Softbank that started with the Acorn Archimedes computer in 1987. ARM chips are ubiquitous, the licenses are relatively cheap, and there’s a lot of ARM expertise out there. The original 2007 iPhone had a Samsung chip with an ARM core inside. iPhone 4 got a custom Apple chip, still with an ARM core, and Apple first used a custom-designed core with iPhone 5 in 2012—Apple more or less designed it from scratch, and only licensed the instruction set from ARM. Last year Apple announced it was moving to its own chips for laptops as well, with the M1 running ARM.
The new kid on the instruction set block is RISC-V. It comes from research at Berkeley dating back to the 1980s, and is completely open and royalty-free, which means there are also many open-source implementations. RISC-V has been slowly gaining traction, especially among Chinese vendors, in part because its openness makes it more resistant to US sanctions, which were preventing Huawei from making ARM chips. There’s no contract required to use RISC-V, so there’s nothing the US Treasury can ban. At the low end of the market, even the few pennies ARM charges per chip can add up, and makers of the cheapest chips can now avoid paying ARM for licensing the instruction set.
ARM initially responded with some good old-fashioned FUD, but has recently started being more open and accessible. It’s now easier to get started using ARM designs without extensive paperwork and negotiations, and it’s easier for professors to teach a chip design class using a real ARM design.
A more interesting development is Intel’s recently announced acquisition of SiFive, a startup founded by three of the Berkeley RISC-V researchers that has created a range of different RISC-V designs, from cheap low-end chips to fast chips that could be used in smartphones or servers. Their top designs are probably only 3 or 4 years behind ARM in terms of performance. Intel opened up its semiconductor fabs to outside customers recently, and is now offering SiFive designs on its 7nm process. Like the Chinese vendors, embracing RISC-V is a way for Intel to gain market share in lower-end markets where ARM currently dominates, while taking advantage of the excitement around RISC-V and without having to come up with completely new designs. (GY)
A very insidery look at why Sebastian Vettel was disqualified from this weekend’s Formula 1 race for not finishing with 1 liter of fuel. (NRB)
A good follow-up to the WITI Technical Debt Edition: Technical Debt Is Not Debt; It’s Not Even Technical (NRB)
For all the How Brands Grow fans out there: What does Byron Sharp’s research really tell us about differentiation? (NRB)
[Sponsored Link] Noah here. Another shout out for my company, Variance. We are building a PLG CRM to help software companies grow their customers. There’s a new post up on the blog about the various organizational antipatterns we see around customer data. Get in touch if you have questions or want to learn more. (NRB)
Thanks for reading,
Noah (NRB) & Colin (CJN) & Guan (GY)
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